Dave Airlie 87229ad9de
drm: micro optimise cache flushing ...
We hit this a lot with i915 and although we'd like to engineer things to hit
it a lot less, this commit at least makes it consume a few less cycles.
from something containing
movzwl 0x0(%rip),%r10d
to
add %r8,%rdx
I only noticed it while using perf to profile something else.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Dave Airlie <airlied@redhat.com >
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87229ad9de